This invention relates to power-on memory self-testing and initialization and particularly to apparatus for performing the memory testing using DMA (Direct Memory Access).
Computer systems periodically test their associated memory, usually when initially applying power. Various patterns are written to and read from the memory to insure proper operation. The final pattern can be an initialization pattern, important when ECC (Error Correction Code) capability is utilized during memory operation.
Such memory tests are usually performed under the control of the main processor as part of a power up initialization routine (POR). As a result, the user must wait until the entire memory check has been performed. As the amount of memory increases, even on small systems, the time required to perform the tests becomes substantial in terms of productivity of the system.
U.S. Pat. No. 4,695,946 (Andreasen et al) shows a computer network having a processor that operates to initialize and to maintain remote diagnostic terminals through system integrity checks and to display data errors or faults in the network. A maintenance program initiates start-up and self-test routines in a sequence order to establish the integrity of the network units. The patent shows memory operations that are program controlled.
U.S. Pat. No. 4,312,066 (Bantz et al) describes a system having a processor that diagnoses or debugs another host processor in order to troubleshoot the latter's hardware and software. The system comprises an interface between the debugging processor and the tested processor to be diagnosed. The tests are performed under program control.
U.S. Pat. No. 4,127,768 (Negi et al) describes diagnostic testing of a central processor provided with a memory coupled to the processor having no requirement for an input device such as a tape or card reader. Local storage of a test program is provided in the processor which, under control of a local control store, transfers the test program to the memory for execution. The central processor is thereby tested to ensure a basic performance level, but under program control.
U.S. Pat. No. 4,030,073 (Armstrong, Jr.) describes an initializing circuit for a digital computer. When the power supply for a digital computer is turned on, the circuit transmits overriding addressing signals. These signals can also be initiated through a console switch and divert the computer from a normal initializing routine to a specially provided initializing routine from the circuit. The program of the initializing circuit includes digital computer instruction sequences for performing preliminary diagnostics and for transferring instructions to a main memory from selected peripherals. When the program terminates, the computer is prepared to process other programs. The diagnostics, however, run under program control.
This invention quickly frees the processor to run other programs by use of a separate hardware system employing the DMA capability of the system to perform the tests.
The technique significantly decreases processor intervention needed for initial power-on memory diagnostics. Page printers, for example, have a large amount of memory so that entire pages can be completely assembled while other pages are being printed. The decreased time between power-on and the execution of application programs significantly increases system productivity.
According to the invention, an address register, a data register, and a termination register are provided. The present termination register can indicate the length of memory to be tested or a termination address at which memory testing is ended.
When the memory is to be tested, e.g., when power is applied to the system, the processor initializes the hardware, perhaps after testing a small, predetermined amount of memory for initial or boot strap operations. The address register is loaded with the address of the first memory location to be tested and the data register is loaded with the data pattern to be written to the memory. Each memory location in succession, beginning at the address in the address register, is written with the pattern stored in the data register by incrementing the address register contents. When the memory under test (MUT) has been written with a given pattern, the apparatus then switches to a read mode, reinitializes the address register, and reads each successive MUT location, comparing the data read with the contents of the data register. If an inequality in the compare operation occurs, then an error interrupt is transmitted to the processor. The location of the error in the MUT can then be read by the processor from the address register because the test operation is halted. If the test is successfully completed, then a termination signal is sent to the processor. Upon receipt of a termination signal, the processor can load the other patterns, the desired initialization pattern being the final pattern.
The data register can supply pseudo-random memory patterns by implementation as a shift register employing modulo-2 summing feedback connections.
Other predetermined data patterns can be generated. For example, binary up-down counters, gray code counters, or special generators for sequences designed to stress the particular memory design can be used. The invention can also be implemented so that the address of the first detected failure is preserved in a special register addressable by the system processor so the test can continue until a second error is encountered.
A variation of the described invention can be used as a memory scrubber. Some types of memories, typically DRAMs (Dynamic Random Access Memories), are subject to temporary errors, usually called soft errors, caused by alpha particles or other phenomena. Soft errors commonly are the result of a change in value of single bits in the memory due to the action of an alpha particle. (An alpha particle is the nucleus of a helium atom and, when accelerated, has sufficient energy to affect the finely structured DRAM cells that store individual bits when collisions occur, sometimes causing the value stored in the cell to be altered.) Occasionally, soft errors may be caused by electrical noise. Soft errors can be rewritten correctly, unlike hard errors which are permanent.
Memory scrubbing is a process whereby a memory location is read using ECC to correct any single bit errors. When the corrected data are written back to the same memory location, any soft errors that occurred on read out will be eliminated.
The system according to the invention automatically executes a memory read command, with ECC, followed by executing a memory write command to the area of memory being scrubbed for soft errors. Better performance results from executing multiple memory read commands into an internal set of registers in the hardware followed by executing multiple memory write commands. The scrubbing operation can be performed by having the hardware read data and write data to the same set of addresses.
The writing and reading operations of the memory are performed using the processor's DMA facility so as to cause as little interference as possible with the processor's operation.